1. Field of the Invention
The present invention generally relates to a method of selectively forming metal layers, more specifically to a method of selectively forming noble metal layers.
2. Description of the Related Art
A back-end-of-line (BEOL) copper interconnect is formed by a damascene or dual damascene process. A damascene process involves creating interconnect lines by first etching trenches or vias in a planar dielectric layer and then filling the trench or vias with a metal, typically copper. In a dual damascene process, which is a conventional semiconductor metallization process, another level is involved, where a series of holes (i.e. contact holes or vias) are etched and filled simultaneously with the trenches. After filling the trenches and/or vias with a metal, the metal and dielectric are planarized by chemical mechanical polishing (CMP), leaving the metal isolated in the trenches and/or vias. A diffusion barrier layer is typically formed before metal deposition in order to prevent diffusion of metal atoms into the dielectric layer.
A dielectric capping layer over copper (Cu), commonly chemical vapor deposition (CVD) SiN, is often used in interconnect metallization schemes. The copper capping layer is usually deposited after a CMP step, which is accomplished after electrochemical deposition of a Cu blanket film and leaves upper surfaces of Cu lines exposed. If no capping layer is used on top of the Cu lines, they would be in intimate contract with the next interlevel dielectric (ILD). This would lead to two primary modes of reliability failure. The first one is leakage current between adjacent Cu lines as Cu atoms would freely diffuse into the ILD, thus degrading the ILD between the Cu lines. The second one is electromigration (EM) related early failure, as Cu atoms would migrate along the poor quality interface between Cu and a dielectric and voids could be formed in the Cu line when electrical current passes through the Cu line. Even with a conventional Cu capping layer, interface-related diffusion (migration of Cu atoms along the interface between, e.g., a Cu line and a Cu capping layer) is one of the leading mechanisms of Cu interconnect failure.
Additional disadvantage of separate blanket CVD dielectric capping layers is an increase of effective k-value for interlevel dielectrics. CVD SiN layer has higher k-value than ILD. Even low-k capping materials such as SiCN and SiC has still higher k-value than the low-k ILD. Thus, the effective k-value of the interlevel dielectric (ILD) increases by addition of the cap layer, relative to the low-k materials that are used as the main dielectric material.
Additionally, adhesion of copper at the via bottom is critical to interconnect reliability because interconnect failure frequently occurs at a via due to migration of copper atoms due to electrical current (EM) or mechanical stress during thermal cycle (stress-induced voiding or SIV). Dielectric layers can exhibit higher thermal expansion than metal, such that the metal in a via is under compressive stress at elevated temperature and under tensile stress at lowered temperature during thermal cycles. Preventing surface or interface migration of copper, which is related to adhesion strength, is important to enhancing copper interconnect reliability. This is especially true for thinner diffusion barriers formed by atomic layer deposition (ALD). In general, an ALD or CVD layer shows weaker adhesion than a PVD layer. On the other hand, an ALD copper diffusion barrier layer is desirable because the thinner barrier layer allows more space for copper in the same via or trench volume and increases conductivity compared to thicker PVD barriers.
One approach to alleviating the abovementioned problems is by selectively forming a copper capping (reliability enhancing) layer over the copper interconnect and/or via forming. A recent innovation in the field selectively deposits CoWP on the top of Cu lines with a CoWP compound by an electroless plating method (e.g., Valery M. Dubin et al., U.S. Pat. No. 5,695,810 “Use of cobalt tungsten phosphide as a barrier material for copper metallization”; Bill Lee, “Electroless CoWP Boosts Copper Reliability, Device Performance” Semiconductor International Jul. 1, 2004, This has been proven to significantly improve interconnect reliability. However, this method has disadvantages, such as many process steps and severe process control and cost issues.
Thus there is a need for a productive, controllable method for forming reliable interfaces in integrated circuit (IC) metallization.